National's Analog to Digital converters employ a new breed of sigma-delta architecture: continuous time sigma-delta (CT∑Δ). The architecture provides high resolution at MHz speeds with significantly improved power consumption efficiency compared to pipelined A/D converters.
The National CT∑Δ ADC is self-clocked. The integrated clock on our A/D converters eliminates the need for expensive, difficult to design clock circuits. We have designed our CT∑Δ ADCs on a true mixed signal CMOS process. This (the CT∑Δ converter also) enables the integration of extra signal path components like input low noise amplifiers (LNA) & programmable gain amplifiers (PGA) and lower overall system costs.
At the heart of a typical ADC is a series of comparators. The skill in designing high performance converters comes in minimizing the number of comparators deployed (reducing power) and controlling component matching characteristics (accuracy/precision). However as CMOS process geometries shrink, it is becoming increasingly challenging to push the dynamic range (resolution) and speed of ADCs with diminishing supply voltage levels.
CT∑Δ ADC technology challenges design assumptions for high resolution ADCs. It recasts the proven sigma-delta (∑Δ) technique as a high speed high resolution alternative to the pipeline solution. Traditionally pipelined ADCs have used sampled discrete time circuits that have to slew continuously on each sample clock edge to track and hold the input signal. This requires very high speed and consequently power hungry circuits. Moving to a continuous time sampling system such as the CTSD, where the input signal is integrated over the full sample period, eliminates the sample and hold amplifier (SHA) resulting in a significant reduction in power consumption.
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